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MAX8855 Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX8855 Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 21 page The power-good, open-drain output for regulator 2 (PWRGD2) is high impedance when VSS2 ≥ 0.54V and VFB2 ≥ 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V, EN2 is low, VVDD or VIN2 is below VUVLO, the thermal-over- load protection is activated, or when VFB2 < 0.9 x VSS2. External Reference Input (REFIN) The MAX8855 has an external reference input. Connect an external reference between 0 and VVDD - 1.6V to REFIN to set the FB1 regulation voltage. To use the inter- nal 0.6V reference, connect REFIN to SS1. When the IC is shut down, REFIN is pulled to GND through 335Ω. Startup and Sequencing The MAX8855 features separate enable inputs (EN1 and EN2) for the two regulators. Driving EN_ high enables the corresponding regulator; driving EN_ low turns the regulator off. Driving both EN1 and EN2 low puts the IC in low-power shutdown mode, reducing the supply current typically to 30nA. The MAX8855 regula- tors power up when the following conditions are met (see Figure 2): • EN_ is logic-high. •VVDD is above the UVLO threshold. •VIN_ is above the UVLO threshold. • The internal reference is powered. • The IC is not in thermal overload (TJ < +165°C). Once these conditions are met, the MAX8855 begins soft-start. FB2 regulates to the voltage at SS2. During soft-start, the SS2 capacitor is charged with a constant 8µA current source so that its voltage ramps up for the soft-start time. See the Setting the Soft-Start Time sec- tion to select the SS2 capacitor for the desired soft-start time. FB1 regulates to the voltage at REFIN. Connect REFIN to SS1 to use the internal reference with soft- start time set independently by the SS1 capacitor (see Figure 3a). Dual, 5A, 2MHz Step-Down Regulator 10 ______________________________________________________________________________________ Figure 2. Startup Control Diagram UVLO UVLO THERM SHDN THERM SHDN REF BIAS GEN REF RDY UVLO VDD RRUVB RRUVB RRUVB EN1 EN2 REG1 ON REG2 ON UVLO UVLO TLIM TLIM IN1 IN2 Figure 3a. Startup and Sequencing Options—Two Independent Output Startup and Shutdown Waveforms EN1 SS2 PWRGD1 EN1 OUT1 OUT2 PWRGD2 EN2 SS1 PWRGD2 VDD REFIN EN2 EN2 PWRGD1 10k Ω 10k Ω EN1 |
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