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MAX19700 Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX19700 Datasheet(HTML) 7 Page - Maxim Integrated Products |
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7 / 37 page  10-Bit, 45Msps, Ultra-Low-Power Analog Front-End _______________________________________________________________________________________ 7 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q-DAC DATA to CLK Rise Setup Time tDSQ Figure 5 (Note 6) 9 ns CLK Fall to I-DAC Data Hold Time tDHI Figure 5 (Note 6) -4 ns CLK Rise to Q-DAC Data Hold Time tDHQ Figure 5 (Note 6) -4 ns CLK Duty Cycle 50 % CLK Duty-Cycle Variation ±15 % Digital Output Rise/Fall Time 20% to 80% 2.6 ns SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6) Falling Edge of CS to Rising Edge of First SCLK Time tCSS 10 ns DIN to SCLK Setup Time tDS 10 ns DIN to SCLK Hold Time tDH 0ns SCLK Pulse-Width High tCH 25 ns SCLK Pulse-Width Low tCL 25 ns SCLK Period tCP 50 ns SCLK to CS Setup Time tCS 10 ns CS High Pulse Width tCSW 80 ns CS High to DOUT Active High tCSD Bit AD0 set 200 ns CS High to DOUT Low (Aux-ADC Conversion Time) tCONV Bit AD0 set, no averaging (see Table 14), fCLK = 45MHz, CLK divider = 16 (see Table 15) 4.27 µs DOUT Low to CS Setup Time tDCS Bit AD0, AD10 set 200 ns SCLK Low to DOUT Data Out tCD Bit AD0, AD10 set 14.5 ns CS High to DOUT High Impedance tCHZ Bit AD0, AD10 set 200 ns MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7) From shutdown to Rx mode, ADC settles to within 1dB SINAD 85.2 Shutdown Wake-Up Time tWAKE,SD From shutdown to Tx mode, DAC settles to within 10 LSB error 28.2 µs From idle to Rx mode with CLK present during idle, ADC settles to within 1dB SINAD 9.8 Idle Wake-Up Time (With CLK) tWAKE,ST0 From idle to Tx mode with CLK present during idle, DAC settles to 10 LSB error 6.4 µs From standby to Rx mode, ADC settles to within 1dB SINAD 13.7 Standby Wake-Up Time tWAKE,ST1 From standby to Tx mode, DAC settles to 10 LSB error 24 µs |
Similar Part No. - MAX19700 |
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Similar Description - MAX19700 |
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