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SN74LVC16245AZQLR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVC16245AZQLR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 18 page SN74LVC16245A 16BIT BUS TRANSCEIVER WITH 3STATE OUTPUTS SCES062N − DECEMBER 1995 − REVISED DECEMBER 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. terminal assignments 12 34 5 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 VCC VCC 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 VCC VCC 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OE NC − No internal connection FUNCTION TABLE (each 8-bit section) INPUTS OPERATION OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation logic diagram (positive logic) To Seven Other Channels 1DIR 1A1 1B1 1OE To Seven Other Channels 2DIR 2A1 2B1 2OE 1 47 24 36 48 2 25 13 Pin numbers shown are for the DGG, DGV, and DL packages. GQL OR ZQL PACKAGE (TOP VIEW) J H G F E D C B A 2 13 4 6 5 K |
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