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LH28F008SCHR-L12 Datasheet(PDF) 7 Page - Sharp Corporation

Part # LH28F008SCHR-L12
Description  Flash Memory 8M (1MB 횞 8)
Download  55 Pages
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Manufacturer  SHARP [Sharp Corporation]
Direct Link  http://sharp-world.com/
Logo SHARP - Sharp Corporation

LH28F008SCHR-L12 Datasheet(HTML) 7 Page - Sharp Corporation

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LHF08CH1
4
Rev. 1.3
Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase
and byte write operations, while the master lock-bit
gates
block
lock-bit
modification.
Lock-bit
configuration operations (Set Block Lock-Bit, Set
Master
Lock-Bit,
and
Clear
Block
Lock-Bits
commands) set and cleared lock-bits.
The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation is
finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY/BY# minimizes
both CPU overhead and system power consumption.
When low, RY/BY# indicates that the WSM is
performing a block erase, byte write, or lock-bit
configuration. RY/BY#-high indicates that the WSM is
ready for a new command, block erase is suspended
(and byte write is inactive), byte write is suspended,
or the device is in deep power-down mode.
The access time is 85ns (tAVQV) over the commercial
temperature range (0°C to +70°C) and VCC supply
voltage range of 4.75V-5.25V. At lower VCC voltages,
the access times are 90ns (4.5V-5.5V), 120ns
(3.0V-3.6V) and 150ns (2.7V-3.6V).
The
Automatic
Power
Savings
(APS)
feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical ICCR current is 1 mA at 5V VCC.
When CE# and RP# pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP# pin is at
GND, deep power-down mode is enabled which
minimizes power consumption and provides write
protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.
The device is available in 40-lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
sharp


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