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R1Q3A3609ABG-60R Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R1Q3A3609ABG-60R Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 26 page R1Q3A3636/R1Q3A3618/R1Q3A3609 Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes Power supply voltage --core VDD 1.7 1.8 1.9 V Power supply voltage --I/O VDDQ 1.4 1.5 VDD V Input reference voltage --I/O VREF 0.68 0.75 0.95 V 1 Input high voltage VIH (DC) VREF + 0.1 VDDQ + 0.3 V 2, 3 Input low voltage VIL (DC) −0.3 VREF − 0.1 V 2, 3 Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 2. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2 Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2 Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS. 3. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters. DC Characteristics (Ta = 0 to +70 °C, VDD = 1.8V ± 0.1V) −30 −33 −40 −50 −60 Parameter Symbol Max Max Max Max Max Unit Notes (×9) IDD 700 650 600 550 500 mA 1, 2, 3 (×18) IDD 750 700 650 600 550 mA 1, 2, 3 Operating supply current (READ / WRITE) (×36) IDD 800 750 700 650 600 mA 1, 2, 3 Standby supply current (NOP) (×9 / ×18 / ×36) ISB1 400 380 350 340 330 mA 2, 4, 5 Parameter Symbol Min Max Unit Test conditions Notes Input leakage current ILI −2 2 µA 10 Output leakage current ILO −5 5 µA 11 Output high voltage VOH (Low) VDDQ −0.2 VDDQ V |IOH| ≤ 0.1 mA 8, 9 VOH VDDQ/2 −0.08 VDDQ/2 +0.08 V Note 6 8, 9 Output low voltage VOL (Low) VSS 0.2 V IOL ≤ 0.1 mA 8, 9 VOL VDDQ/2 −0.08 VDDQ/2 +0.08 V Note 7 8, 9 Notes: 1. All inputs (except ZQ, VREF) are held at either VIH or VIL. 2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. 3. Operating supply currents are measured at 100% bus utilization. 4. All address / data inputs are static at either VIN > VIH or VIN < VIL. 5. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. 6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I standards. 10. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). 11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled. REJ03C0295-0003 Rev.0.03 Jul. 31, 2007 Page 11 of 24 |
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