R1Q2A3636/R1Q2A3618/R1Q2A3609

Bus Cycle State Diagram

Read Port NOP

Read Double

Load New

Read Address

Power Up

/R = H

Write Port NOP

/W = H

Supply voltage

provided

Supply voltage

provided

/R = L

Always

/R = L

/R = H

Write Double

at /K

↑

Load New

Write Address

at /K

↑

/W = L

Always

/W = L

/W = H

Notes: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order

is always fixed as: xxx…xxx+0, xxx…xxx+1.

Bus cycle is terminated at the end of this sequence (burst count = 2).

2. Read and write state machines can be active simultaneously.

3. State machine control timing sequence is controlled by K.

REJ03C0294-0003 Rev.0.03 Jul. 31, 2007

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