DS26303_07 datasheet(2/101 Pages) DALLAS

Part #	DS26303

Description	3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit

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Manufacturer	DALLAS [Dallas Semiconductor]

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

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TABLE OF CONTENTS

1

DETAILED DESCRIPTION ...............................................................................................................6

2

TELECOM SPECIFICATIONS COMPLIANCE.................................................................................7

3

BLOCK DIAGRAMS .........................................................................................................................9

4

PIN DESCRIPTION .........................................................................................................................11

4.1

HARDWARE AND HOST PORT OPERATION ......................................................................................20

4.1.1

Hardware Mode................................................................................................................................... 20

4.1.2

Serial Port Operation .......................................................................................................................... 21

4.1.3

Parallel Port Operation........................................................................................................................ 22

4.1.4

Interrupt Handling ............................................................................................................................... 22

5

REGISTERS ....................................................................................................................................24

5.1

REGISTER DESCRIPTION ...............................................................................................................29

5.1.1

Primary Registers................................................................................................................................ 29

5.1.2

Secondary Registers........................................................................................................................... 38

5.1.3

Individual LIU Registers ...................................................................................................................... 40

5.1.4

BERT Registers .................................................................................................................................. 47

6

FUNCTIONAL DESCRIPTION........................................................................................................54

6.1

POWER-UP AND RESET .................................................................................................................54

6.2

MASTER CLOCK ............................................................................................................................54

6.3

TRANSMITTER ...............................................................................................................................55

6.3.1

Transmit Line Templates .................................................................................................................... 56

6.3.2

LIU Transmit Front-End ...................................................................................................................... 58

6.3.3

Dual-Rail Mode ................................................................................................................................... 59

6.3.4

Single-Rail Mode................................................................................................................................. 59

6.3.5

Zero Suppression—B8ZS or HDB3 .................................................................................................... 59

6.3.6

Transmit Power-Down ........................................................................................................................ 59

6.3.7

Transmit All Ones................................................................................................................................ 59

6.3.8

Driver Fail Monitor............................................................................................................................... 59

6.4

RECEIVER.....................................................................................................................................59

6.4.1

Peak Detector and Slicer .................................................................................................................... 59

6.4.2

Clock and Data Recovery ................................................................................................................... 59

6.4.3

Loss of Signal...................................................................................................................................... 60

6.4.4

AIS ...................................................................................................................................................... 60

6.4.5

Bipolar Violation and Excessive Zero Detector................................................................................... 62

6.4.6

LIU Receiver Front-End ...................................................................................................................... 62

6.5

HITLESS-PROTECTION SWITCHING (HPS) ......................................................................................62

6.6

JITTER ATTENUATOR.....................................................................................................................64

6.7

G.772 MONITOR ...........................................................................................................................65

6.8

LOOPBACKS..................................................................................................................................65

6.8.1

Analog Loopback ................................................................................................................................ 65

6.8.2

Digital Loopback.................................................................................................................................. 65

6.8.3

Remote Loopback ............................................................................................................................... 66

6.8.4

Dual Loopback .................................................................................................................................... 67

6.9

BERT...........................................................................................................................................68

6.9.1

Configuration and Monitoring.............................................................................................................. 68

6.9.2

BERT Interrupt Handling..................................................................................................................... 69

6.9.3

Receive Pattern Detection .................................................................................................................. 69

6.9.4

Transmit Pattern Generation............................................................................................................... 71

7

JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................................72

7.1

TAP CONTROLLER STATE MACHINE ..............................................................................................73

7.1.1

Test-Logic-Reset................................................................................................................................. 73

7.1.2

Run-Test-Idle ...................................................................................................................................... 73

7.1.3

Select-DR-Scan .................................................................................................................................. 73

7.1.4

Capture-DR ......................................................................................................................................... 73

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