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DSPIC33FJ128GP310 Datasheet(PDF) 6 Page - Microchip Technology |
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DSPIC33FJ128GP310 Datasheet(HTML) 6 Page - Microchip Technology |
6 / 10 page dsPIC33F DS80279B-page 6 © 2006 Microchip Technology Inc. 9. Module: SPI Module in Frame Master Mode The SPI module will fail to generate frame syn- chronization pulses when configured in the Frame Master mode (FRMEN = 1, SPIFSD = 0). How- ever, the module functions correctly in Frame Slave mode. Work around If DMA is not being used, manually drive the SSx pin (x = 1 or 2) high using the associated PORT register, and then drive it low after the required 1 bit-time pulse width. This operation needs to be performed when the transmit buffer is written. If DMA is being used, and if no other peripheral modules are using DMA transfers, use a timer interrupt to periodically generate the frame syn- chronization pulse (using the method described above) after every 8 or 16 bit periods (depending on the data word size, configured using the MODE16 bit). 10. Module: SPI Module in Slave Select Mode The SPI module Slave Select functionality (enabled by setting SSEN = 1) will not function cor- rectly. Whether the SSx pin (x = 1 or 2) is high or low, the SPI data transfer will be completed and an interrupt will be generated. Work around If DMA is not being used, manually poll the SSx pin state in the SPI interrupt by reading the associated LAT bit: • If the LAT bit is ‘0’, then perform the required data read/write. • If the LAT bit is ‘1’, then clear the SPI interrupt flag (SPIxIF), perform a dummy read of the SPIxBUF register, and return from the Interrupt Service Routine. If DMA is being used, there is no work around. 11. Module: SPI Module The SMP bit (SPIxCON1<9>, where x = 1 or 2) does not have any effect when the SPI module is configured for a 1:1 prescale factor in Master mode. In this mode, whether the SMP bit is set or cleared, the data is always sampled at the end of data output time. Work around If sampling at the middle of data output time is required, then configure the SPI module to use a clock prescale factor other than 1:1 using the PPRE<1:0> and SPRE<2:0> bits in the SPIxCON1 register. 12. Module: ECAN Module If multiple ECAN transmit buffers are queued for transmission (multiple TXREQ bits are set to ‘1’ simultaneously), then the message transmissions from the enabled buffers may interfere with one another. As a result, incorrect ID and data transmissions will occur intermittently. Work around Enable only one transmit buffer for transmission at any given time. In the user application, this can be ensured by checking that all other TXREQn bits are clear before setting the TXREQn bit corresponding to the buffer that is to be transmitted. 13. Module: ECAN Module Under specific conditions, the first five bits of a transmitted identifier may not match the value in the transmit buffer SID. If the ECAN module detects a Start-of-Frame (SOF) in the third bit of interframe space and if a message to be transmit- ted is pending, the first five bits of the transmitted identifier may be corrupted. Work around None. 14. Module: ECAN Module Loopback Mode The ECAN module (ECAN1 or ECAN2) does not function correctly in Loopback mode. Work around Do not use Loopback mode. 15. Module: I2C Module The Bus Collision Status bit (BCL) does not get set when a bus collision occurs during a Restart or Stop event. However, the BCL bit gets set when a bus collision occurs during a Start event. Work around None. |
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