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DSPIC33FJ64GP710 Datasheet(PDF) 2 Page - Microchip Technology |
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DSPIC33FJ64GP710 Datasheet(HTML) 2 Page - Microchip Technology |
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2 / 10 page  dsPIC33F DS80279B-page 2 © 2006 Microchip Technology Inc. 7. Output Compare Module The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. 8. Output Compare Module in PWM Mode The output compare module will miss one com- pare event when the duty cycle register value is updated from 0x0000 to 0x0001. 9. SPI Module in Frame Master Mode The SPI module will fail to generate frame synchronization pulses in Frame Master mode. 10. SPI Module in Slave Select Mode The SPI module Slave Select functionality will not work correctly. 11. SPI Module The SMP bit does not have any effect when the SPI module is configured for a 1:1 prescale factor in Master mode. 12. ECAN™ Module ECAN transmissions may be incorrect if multiple transmit buffers are simultaneously queued for transmission. 13. ECAN Module Under specific conditions, the first five bits of a transmitted identifier may not match the value in the transmit buffer ID register. 14. ECAN Module Loopback Mode The ECAN module (ECAN1 or ECAN2) does not function correctly in Loopback mode. 15. I2C™ Module The bus collision status bit does not get set when a bus collision occurs during a Restart or Stop event. 16. INT0, ADC and Sleep/Idle Mode ADC event triggers from the INT0 pin will not wake-up the device from Sleep or Idle mode if the SMPI bits are non-zero. 17. Doze Mode and Traps The address error trap, stack error trap, math error trap and DMA error trap will not wake-up a device from Doze mode. 18. JTAG Programming JTAG programming does not work. The following sections will describe the errata and work around to these errata, where they may apply. 1. Module: Oscillator: Doze Mode Enabling Doze mode slows down the CPU but allows peripherals to run at full speed. When the CPU clock is slowed down by enabling Doze mode (CLKDIV<11> = 1), any writes to a peripheral SFR can cause other updates to that register to cease to function for the duration of the current CPU clock cycle. This is only an issue if the CPU attempts to write to the same register as a peripheral while in Doze mode. For instance, if the ADC module is active and Doze mode is enabled, the main program should avoid writing to ADCCONx registers because these reg- isters are being used by the ADC module. If the CPU does make writes before the ADC module does, then any attempts by the ADC module to write to these registers will fail. Work around In Doze mode, avoid writing code that will modify SFRs which may be written to by enabled peripherals. |
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