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TDA8755T Datasheet(PDF) 11 Page - NXP Semiconductors |
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TDA8755T Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 1995 Mar 09 11 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 Fig.6 Timing definition for set-up and hold times (HREF signal). The output data is valid 4 clock periods after HREF goes HIGH. handbook, full pagewidth MLA732 - 1 CLK HREF output data output data valid 12 3 4 t h t su sample N N 4 N 3 N 2 N 1 N sample N sample N 4 5 Fig.7 Timing diagram (HREF signal). When the HREF period is a multiple of 4 clock periods, the output data is valid without any clock delay. The internal circuit always gives an internal delay of 4 clock periods as illustrated in Fig.6. handbook, full pagewidth MLA731 - 1 CLK HREF output data output data valid 4 clock periods (T ) sample N sample N 4 x T N 4 N 3 N 3 sample N 4 (T 1) clk clk clk |
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