UL635H256

7

March 31, 2006

STK Control #ML0059

Rev 1.0

Nonvolatile Memory Operations

Mode Selection

E

W

A13 - A0

(hex)

Mode

I/O

Power

Notes

H

X

X

Not Selected

Output High Z

Standby

L

H

X

Read SRAM

Output Data

Active

m

L

L

X

Write SRAM

Input Data

Active

LH

0E38

31C7

03E0

3C1F

303F

0FC0

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile STORE

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

k, l

k, l

k, l

k, l

k, l

k, l

LH

0E38

31C7

03E0

3C1F

303F

0C63

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile RECALL

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

k, l

k, l

k, l

k, l

k, l

k, l

k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL

cycle tables and diagrams for further details.

The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.

l:

While there are 15 addresses on the UL635H256, only the lower 14 are used to control software modes.

Activation of nonvolatile cycles does not depend on the state of G.

m: I/O state assumes that G

No.

PowerStore

Power Up RECALL

Symbol

Conditions

Min.

Max.

Unit

Alt.

IEC

650

μs

the power supply decay

rate has to be smaller

start of the STORE

operation

10

ms

26

Time allowed to Complete SRAM

500

ns

Low Voltage Trigger Level

2.4

2.7

V

n: