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UL631H256S2K35 Datasheet(PDF) 10 Page - Simtek Corporation |
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UL631H256S2K35 Datasheet(HTML) 10 Page - Simtek Corporation |
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10 / 13 page  UL631H256 10 March 31, 2006 STK Control #ML0057 Rev 1.0 Device Operation The UL631H256 has two separate modes of operation: SRAM mode and nonvolatile mode. The memory ope- rates in SRAM mode as a standard fast static RAM. Data is transferred In nonvolatile mode from SRAM to EEPROM shadow (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. SRAM READ The UL631H256 performs a READ cycle whenever E and G are LOW while W is HIGH. The address speci- fied on pins A0 - A14 determines which of the 32768 data bytes will be accessed. When the READ is initia- ted by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Noise Consideration The UL631H256 is a high speed memory and therefore must have a high frequency bypass capacitor of appro- ximately 0.1 μF connected between VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal carefull routing of power, ground and signals will help prevent noise pro- blems. Software Nonvolatile STORE The UL631H256 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the UL631H256 implements nonvolatile operation while remaining compatible with standard 32K x 8 SRAMs. During the STORE cycle, an erase of the pre- vious nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the STORE cycle the following READ sequence must be performed: 1. Read addresses 0E38 (hex) Valid READ 2. Read addresses 31C7 (hex) Valid READ 3. Read addresses 03E0 (hex) Valid READ 4. Read addresses 3C1F (hex) Valid READ 5. Read addresses 303F (hex) Valid READ 6. Read addresses 0FC0 (hex) Initiate STORE Cycle Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. Software Nonvolatile RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ opera- tions must be performed: 1. Read addresses 0E38 (hex) Valid READ 2. Read addresses 31C7 (hex) Valid READ 3. Read addresses 03E0 (hex) Valid READ 4. Read addresses 3C1F (hex) Valid READ 5. Read addresses 303F (hex) Valid READ 6. Read addresses 0C63 (hex) Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Automatic Power Up RECALL On power up, once VCC exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated. The voltage on the VCC pin must not drop below VSWITCH once it has risen above it in order for the |
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