5-4

FAST AND LS TTL DATA

SN54/74LS160A

• SN54/74LS161A

SN54/74LS162A

• SN54/74LS163A

LS162A and LS163A

Sb l

P

Limits

Ui

T

C

di i

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

54

0.7

V

Guaranteed Input LOW Voltage for

VIL

Input LOW Voltage

74

0.8

V

pg

All Inputs

VIK

Input Clamp Diode Voltage

– 0.65

– 1.5

V

VCC = MIN, IIN = – 18 mA

VOH

Output HIGH Voltage

54

2.5

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

VOH

Output HIGH Voltage

74

2.7

3.5

V

CC

, OH

,

IN

IH

or VIL per Truth Table

VOL

Output LOW Voltage

54, 74

0.25

0.4

V

IOL = 4.0 mA

VCC = VCC MIN,

VIN =VIL or VIH

VOL

Output LOW Voltage

74

0.35

0.5

V

IOL = 8.0 mA

VIN = VIL or VIH

per Truth Table

IIH

Input HIGH Current

Data, CEP, Clock

PE, CET, SR

20

40

µA

VCC = MAX, VIN = 2.7 V

IIH

Data, CEP, Clock

PE, CET, SR

0.1

0.2

mA

VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

Data, CEP, Clock, PE, SR

CET

– 0.4

– 0.8

mA

VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1)

–20

– 100

mA

VCC = MAX

ICC

Power Supply Current

Total, Output HIGH

Total, Output LOW

31

32

mA

VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Sb l

P

Limits

Ui

T

C

di i

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Clock Frequency

25

32

MHz

V5 0 V

tPLH

tPHL

Propagation Delay

Clock to TC

20

18

35

35

ns

V5 0 V

tPLH

tPHL

Propagation Delay

Clock to Q

13

18

24

27

ns

VCC = 5.0 V

CL = 15 pF

tPLH

tPHL

Propagation Delay

CET to TC

9.0

9.0

14

14

ns

tPHL

MR or SR to Q

20

28

ns