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UL635H256SC35G1 Datasheet(PDF) 11 Page - Simtek Corporation |
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UL635H256SC35G1 Datasheet(HTML) 11 Page - Simtek Corporation |
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11 / 14 page  UL635H256 11 March 31, 2006 STK Control #ML0059 Rev 1.0 Device Operation The UL635H256 has two separate modes of operation: SRAM mode and nonvolatile mode. The memory ope- rates in SRAM mode as a standard fast static RAM. Data is transferred in nonvolatile mode from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. STORE cycles may be initiated under user control via a software sequence and are also automatically initiated when the power supply voltage level of the chip falls below VSWITCH. RECALL operations are automatically initiated upon power up and may also occur when the VCC rises above VSWITCH, after a low power condition. RECALL cycles may also be initiated by a software sequence. SRAM READ The UL635H256 performs a READ cycle whenever E and G are LOW and W is HIGH. The address specified on pins A0 - A14 determines which of the 32768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the out- puts will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis (W) after W goes LOW. Automatic STORE The UL635H256 uses the intrinsic system capacitance to perform an automatic STORE on power down. As long as the decay rate from the system power supply is smaller than 15 Vs-1 the UL635H256 will safely and automatically STORE the SRAM data in EEPROM on power down. In order to prevent unneeded STORE operations, auto- matic STORE will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. Automatic RECALL During power up, an automatic RECALL takes place. At a low power condition (power supply voltage < VSWITCH) an internal RECALL request may be latched. As soon as power supply voltage exceeds the sense voltage of VSWITCH, a requested RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the UL635H256 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 k Ω resistor should be connected between W and power supply voltage. Software Nonvolatile STORE The UL635H256 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the UL635H256 implements nonvolatile operation while remaining compatible with standard 32K x 8 SRAMs. During the STORE cycle, an erase of the pre- vious nonvolatile data is performed first, followed by a parallel programming of all the nonvolatile elements. Once a STORE cycle is initiated, further inputs and out- puts are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted. To initiate the STORE cycle the following READ sequence must be performed: 1. Read addresses 0E38 (hex) Valid READ 2. Read addresses 31C7 (hex) Valid READ 3. Read addresses 03E0 (hex) Valid READ 4. Read addresses 3C1F (hex) Valid READ 5. Read addresses 303F (hex) Valid READ 6. Read addresses 0FC0 (hex) Initiate STORE Cycle Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. |
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Similar Description - UL635H256SC35G1 |
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