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PIC18FXX2 Datasheet(PDF) 70 Page - Microchip Technology |
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PIC18FXX2 Datasheet(HTML) 70 Page - Microchip Technology |
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70 / 332 page  PIC18FXX2 DS39564C-page 68 © 2006 Microchip Technology Inc. 6.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. 6.7 Operation During Code Protect Data EEPROM memory has its own code protect mechanism. External Read and Write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal Data EEPROM, regardless of the state of the code protect configuration bit. Refer to “Special Features of the CPU” (Section 19.0) for additional information. 6.8 Using the Data EEPROM The data EEPROM is a high endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program vari- ables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, cali- bration, etc.) should be stored in FLASH program memory. A simple data EEPROM refresh routine is shown in Example 6-3. EXAMPLE 6-3: DATA EEPROM REFRESH ROUTINE Note: If data EEPROM is only used to store con- stants and/or data that changes rarely, an array refresh is likely not required. See specification D124. clrf EEADR ; Start at address 0 bcf EECON1,CFGS ; Set for memory bcf EECON1,EEPGD ; Set for Data EEPROM bcf INTCON,GIE ; Disable interrupts bsf EECON1,WREN ; Enable writes Loop ; Loop to refresh array bsf EECON1,RD ; Read current address movlw 55h ; movwf EECON2 ; Write 55h movlw AAh ; movwf EECON2 ; Write AAh bsf EECON1,WR ; Set WR bit to begin write btfsc EECON1,WR ; Wait for write to complete bra $-2 incfsz EEADR,F ; Increment address bra Loop ; Not zero, do it again bcf EECON1,WREN ; Disable writes bsf INTCON,GIE ; Enable interrupts |
Similar Part No. - PIC18FXX2_06 |
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Similar Description - PIC18FXX2_06 |
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