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TPS65167

SLVS760A – APRIL 2007 – REVISED MAY 2007

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

FBP

20

Feedback of the positive charge pump

POUT

21

Output of the positive charge pump converter

VGH

22

Output of the high voltage switch and gate shaping function block

DRN

23

Termination of the low side switch of the gate voltage shaping block

Control input for the gate voltage shaping block. Connect this pin to REGOUT if the gate voltage shaping

CTRL

24

I

function is not used.

Connecting a capacitor from this pin to GND allows to set the delay time between the boost converter Vs and

GDLY

25

O

VGH. Note that VGH is controlled by CTRL as well.

This is the enable pin of the boost converter Vs, negative charge pump VGL and positive charge pump

EN

26

I

POUT. This pin is a dual function pin. EN can be held high if no start-up delay is desired or a capacitor can

be connected to this pin. The capacitor determines the start-up delay time.

Logic control input to force the device into High Voltage Stress Test. With HVS = low the high voltage stress

HVS

27

I

test disabled. With HVS = high the high voltage stress test is enabled.

This resistor sets the voltage of the boost converter Vs when the High Voltage Stress test is enabled. (HVS =

RHVS

28

I/O

high). With HVS = high the RHVS pin is pulled to GND which sets the voltage for the boost converter during

High Voltage Stress. When HVS is disabled (HVS = low) the RHVS pin is high impedance.

FB

29

I

Feedback of the boost converter Vs

Compensation for the regulation loop of the boost converter generating Vs. Typically a 22 nF compensation

COMP

30

I/O

capacitor is connected to this pin.

This is the output of the internal device temperature sensor. The output voltage is proportional to the chip

TEMP

31

O

temperature.

PGND

32, 33

Power Ground for the boost converter Vs

SW

34, 35

I/O

Switch pin of the boost converter generating Vs

GD

36

I/O

Gate drive. This pin controls the external isolation MOSFET

GND

37

Analog Ground for the internal reference

AVIN

38

I

Analog input voltage of the device. Bypass this pin with a 0.47

µF bypass capacitor

FBLDO

39

I

Feedback of the LDO controller

BASE

40

I/O

BASE drive of the external pnp transistor.

PowerPAD™

Analog GND for the internal reference

6

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