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TDA8703 Datasheet(PDF) 9 Page - NXP Semiconductors |
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TDA8703 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 18 page 1996 Aug 26 9 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 Notes 1. The circuit has two clock inputs CLK and CLK. There are four modes of operation: a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling on the LOW-to-HIGH transition of the input clock signal. b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling on the HIGH-to-LOW transition of the input clock signal. c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V (peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition. d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF capacitor. 2. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 2 ns. 3. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at the input). 4. Low frequency ramp signal (VVI(p-p) = 1.8 V and fi = 15 kHz) combined with a sinewave input voltage (VVI(p-p) = 0.5 V, fi = 4.43 MHz) at the input. 5. Supply voltage ripple rejection: a) SVRR1; variation of the input voltage producing output code 127 for supply voltage variation of 1 V: SVRR1 = 20 log ( ∆VVI(127) / ∆VCCA) b) SVRR2; relative variation of the full-scale range of analog input for a supply voltage variation of 1 V: SVR2 = { ∆(VVI(0) − VVI(255))/(VVI(0) − VVI(255))} ÷∆VCCA. 6. Full-scale sinewave (fi = 4.4 MHz; fCLK; fCLK = 27 MHz). 7. Output data acquisition: a) Output data is available after the maximum delay of tdHL and tdLH. |
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