Micrel, Inc.

SY89230U

July. 18, 2007

M9999-071807-A

3

Pin Description

Pin Number

Pin Name

Pin Function

1, 4

IN, /IN

Differential Input: This input pair is the differential signal input to the device,

which accepts AC- or DC-coupled signal as small as 100mV. The input internally

terminates to a VT pin through 50Ω and has level shifting resistors of 3.72 kΩ to

VCC. This allows a wide input voltage range from VCC to GND. See Figure 3a,

Simplified Differential Input Stage for details. Note that this input will default to a

valid (either HIGH or LOW) state if left open. See “Input Interface Applications”

subsection.

2

VT

Input Termination Center-Tap: Each side of the differential input pair terminates

to the VT pin. The VT pin provides a center-tap for the input (IN, /IN) to a

termination network for maximum interface flexibility. See “Input Interface

Applications” section for more details.

3

VREF-AC

inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF

low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is

only intended to drive its respective VT pin. Maximum sink/source current is

±0.5mA. See “Input Interface Applications” subsection.

5

EN

Single-ended Input: This TTL/CMOS-compatible input disables and enables the

output. It is internally connected to a 25kΩ pull-up resistor and will default to a

logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH.

EN being synchronous, outputs will be enabled/disabled after a rising and a

6

/MR

Single-ended Input: This TTL/CMOS-compatible input, when pulled LOW,

asynchronously sets Q output LOW and /Q output HIGH. Note that this input is

internally connected to a 25kΩ pull-up resistor and will default to logic HIGH

7

NC

No Connect

8, 13

VCC

Positive Power Supply: Bypass with 0.1µF in parallel with 0.01µF low ESR

12, 9

Q, /Q

Differential Output: The LVPECL output swing is typically 800mV and is

function.

10, 11, 14,15

GND,

Exposed Pad

Ground: Ground and exposed pad must be connected to a ground plane that is

the same potential as the ground pins.

16

DIV_SEL

Single-ended Input: This TTL/CMOS-compatible input selects divide-by-3 when

pulled LOW and divide-by-5 when pulled HIGH. Note that this input is internally

connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left

Truth Table

Inputs

Outputs

DIV_SEL

EN

/MR

Q

/Q

X

X

0

0

1

0

1

1

1

1

1

X

0

1

0

1