SY89230UMG datasheet(7/15 Pages) MICREL

Part #	SY89230UMG

Description	3.2GHz Precision, LVPECL 첨3, 첨5 Clock Divider

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Manufacturer	MICREL [Micrel Semiconductor]

Direct Link	http://www.micrel.com

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Micrel, Inc.

SY89230U

July. 18, 2007

M9999-071807-A

hbwhelp@micrel.com or (408) 955-1690

7

Functional Description

Output Duty Cycle Equation

For divide by 3, output Duty Cycle is:

3

100

1

X

+

For divide by 5, output Duty Cycle is:

5

100

2

X

+

X = input Duty Cycle

Enable (EN)

EN is a synchronous TTL/CMOS-compatible input that

enables/disables the outputs based on the input to

this pin. Internal 25kΩ pull-up resistor defaults the

input to logic HIGH if left open. Input switching

threshold is VCC/2.

The Enable function operates as follows:

1. The

enable/disable

function

is

synchronous so that the clock outputs will

be enabled or disabled following a rising

and a falling edge of the input clock when

switching from EN = LOW to EN = HIGH.

However, when switching from EN = HIGH

to EN = LOW, the clock outputs will be

disable following an input clock rising edge

and an output clock falling edge.

2. The

enable/disable

function

always

guarantees the full pulse width at the

output before the clock outputs are

disabled, non-depending on the divider

ratio. Refer to Figure 1b for examples.

Divider Operation

The divider operation uses both the rising and falling

edge of the input clock. For divide by 3, the falling

edge of the second input clock cycle will determine

the falling edge of the output. For divide by 5, the

falling edge of the third input clock cycle. Refer to

Figure 1c.

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