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© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 3.0 — 18 July 2007

2 of 7

NXP Semiconductors

MF1 IC S20 05

Sawn bumped 120µm wafer addendum

500 nm / 600 nm

3.5 Au bump

> 99.9% pure Au

35 – 80 HV 0.005

> 70 MPa

18

µm

– within a die:

± 2

µm

– within a wafer:

± 3

µm

– wafer to wafer:

± 4

µm

± 1.5

µm

104 x 104

µm

89 x 104

µm

± 5

µm

sputtered TiW

Remark: Substrate is connected to VSS.

3.6 Fail die identification

Electronic wafer mapping covers the electrical test results and additionally the results of

mechanical/ visual inspection.

No inkdots are applied.

1.Pads VSS and TESTIO are disconnected when wafer is sawn.