HMXADC9225NZN datasheet(8/11 Pages) HONEYWELL

Part #	HMXADC9225NZN

Description	Radiation Hardened 12-Bit, 20 MSPS Monolithic A/D Converter

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Manufacturer	HONEYWELL [Honeywell Solid State Electronics Center]

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HMXADC9225

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SIGNAL-TO-NOISE AND DISTORTION

(S/N+D, SINAD) RATIO

S/N+D is the ratio of the rms value of the measured

input signal to the rms sum of all other spectral

components below the Nyquist frequency, including

harmonics but excluding dc. The value for S/N+D is

expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of

the number of bits. Using the following formula,

N

= (SINAD – 1.76)/6.02

it is possible to get a measure of performance

expressed as N, the effective number of bits. Thus,

effective number of bits for a device for sine wave

inputs at a given input frequency can be calculated

directly from its measured SINAD.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input

signal and is expressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input

signal to the rms sum of all other spectral components

below the Nyquist frequency, excluding the first six

harmonics and dc. The value for SNR is expressed in

decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

SFDR is the difference in dB between the rms

amplitude of the input signal and the peak spurious

signal.

TYPICAL DNL (10MSPS)

TYPICAL INL (10MSPS)

FUNCTIONAL DESCRIPTION

The HMXADC9225 is a complete high performance

single-supply 12-bit ADC. The analog input range of the

HMXADC9225 is highly flexible allowing for either

single-ended or differential inputs of varying amplitudes

that can be AC or DC coupled.

It utilizes four-stage pipeline architecture with a

wideband input sample-and-hold amplifier (SHA)

implemented on an SOI CMOS process. Each stage of

the pipeline, excluding the last stage, consists of a low-

resolution flash A/D connected to a switched capacitor

DAC and interstage residue amplifier (MDAC). The

residue amplifier amplifies the difference between the

reconstructed DAC output and the flash input for the

next stage in the pipeline. One bit of redundancy is

used in each of the stages to facilitate digital correction

of flash errors. The last stage simply consists of a flash

A/D.

The pipeline architecture allows a greater throughput

rate at the expense of pipeline delay or latency. This

means that while the converter is capable of capturing a

new input sample every clock cycle, it actually takes

three clock cycles for the conversion to be fully

processed and appear at the output. This latency is not

a concern in most applications. The digital output is

latched into an output buffer to drive the output pins.

The HMXADC9225 uses both edges of the clock in its

internal timing circuitry (see Timing Diagram and

specification page for exact timing requirements). The

A/D samples the analog input on the rising edge of the

clock input. During the clock low time (between the

falling edge and rising edge of the clock), the input SHA

is in the sample mode; during the clock high time it is in

hold. System disturbances just prior to the rising edge

of the clock and/or excessive clock jitter may cause the

input SHA to acquire the wrong value, and should be

minimized.

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HMXADC9225NZN Datasheet(PDF) 8 Page - Honeywell Solid State Electronics Center

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