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AZP92 Datasheet(PDF) 2 Page - Arizona Microtek, Inc |
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AZP92 Datasheet(HTML) 2 Page - Arizona Microtek, Inc |
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2 / 7 page  AZP92 April 2007 REV - 3 www.azmicrotek.com 2 TIMING DIAGRAM SIGNAL DESCRIPTION PIN/PAD FUNCTION D/D ¯ Data Inputs Q/Q ¯ Data Outputs VBB Reference Voltage Output BIAS Input Bias Return EN Enable/Reset Input EN-SEL Enable Logic Select DIV-SEL Divide Ratio Select VEE Negative Supply VCC Positive Supply ENABLE TRUTH TABLE EN-SEL EN Q Q ¯ NC NC CMOS Low or VEE CMOS High, VCC or NC Low Data High Data VEE VEE CMOS Low, VEE or NC CMOS High or VCC Low Data High Data 20k Ω to V EE 20k Ω to V EE PECL Low, VEE or NC PECL High or VCC Data Low Data High Q D (EN-SEL CONNECTED TO VEE VIA 20k RESISTOR) (EN-SEL OPEN OR CONNECTED TO VEE) EN (PECL) (CMOS) (DIV-SEL CONNECTED TO VEE) (DIV-SEL OPEN) EN Q DIVIDE TRUTH TABLE DIV-SEL DIVIDE RATIO NC ÷1 VEE 1 ÷2 1 DIV-SEL connection must be ≤1Ω. |
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