6

Figure 7. Recommended Decoupling and Termination Circuits

Figure 6. Bit Error Rate vs. Relative Receiver

Input Optical Power.

Transceiver Jitter Performance

The Agilent 1300 nm

transceivers are designed to

operate per the system jitter

allocations stated in Tables E1

of Annexes E of the FDDI

PMD and LCF-PMD standards.

The Agilent 1300 nm

transmitters will tolerate the

worst case input electrical

jitter allowed in these tables

without violating the worst

case output jitter requirements

of Sections 8.1 Active Output

Interface of the FDDI PMD and

LCF-PMD standards.

The Agilent 1300 nm receivers

will tolerate the worst case

input optical jitter allowed in

Sections 8.2 Active Input

Interface of the FDDI PMD and

LCF-PMD standards without

violating the worst case output

electrical jitter allowed in the

Tables E1 of the Annexes E.

The jitter specifications stated

i n the following 1300 nm

transceiver specification tables

are derived from the values in

Tables E1 of Annexes E. They

represent the worst case jitter

contribution that the trans-

ceivers are allowed to make to

the overall system jitter

without violating the Annex E

allocation example. In practice

the typical contribution of the

Agilent transceivers is well

below these maximum allowed

amounts.

Recommended Handling Precautions

Agilent recommends that

normal static precautions be

taken in the handling and

assembly of these transceivers

to prevent damage which may

be induced by electrostatic

discharge (ESD). The AFBR-

5800 series of transceivers

meet MIL-STD-883C Method

3015.4 Class 2 products.

Care should be used to avoid

shorting the receiver data or

signal detect outputs directly

to ground without proper

current limiting impedance.

-6

4

RELATIVE INPUT OPTICAL POWER - dB

-4

2

-2

0

CONDITIONS:

1. 155 MBd

2. PRBS 2

3. CENTER OF SYMBOL SAMPLING

4. T

5. V

6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.

CENTER OF SYMBOL

AFBR-5803 SERIES

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NO INTERNAL CONNECTION

NO INTERNAL CONNECTION

AFBR-5803Z

TOP VIEW

V

EE

RD

RD

SD

V

CC

V

CC

TD

TD

V

EE

123

45

6789

C1

C2

L1

L2

R2

R3

R1

R4

C5

C3

C4

R9

R10

V

AT V

TRANSCEIVER

R5

R7

R6

R8

C6

RD

RD

SD

V

CC

TD

TD

TERMINATION

AT PHY

DEVICE

INPUTS

NOTES:

THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT

OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT

BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.

R1 = R4 = R6 = R8 = R10 = 130 OHMS FOR +5.0 V OPERATION, 82 OHMS FOR +3.3 V OPERATION.

R2 = R3 = R5 = R7 = R9 = 82 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.

C1 = C2 = C3 = C5 = C6 = 0.1 µF.

C4 = 10 µF.

L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.

TERMINATION

AT TRANSCEIVER

INPUTS

Rx

Rx

Tx

Tx

V

CC

V

CC

Rx

Tx