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STSLVDSP27 Datasheet(PDF) 10 Page - STMicroelectronics |
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STSLVDSP27 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 23 page Electrical characteristics STSLVDSP27 10/23 Table 8. Parallel switching characteristics (DPLL = "ON", RT = 100Ω ±1%, CL = 10pF, over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25°C and VDD = 3.0V, VIO = 1.8V) Symbol Parameter Test Conditions Min. Typ. Max. Unit trVOD Rise time differential output voltage (20% to 80%) (Figure 4.) trDIN = 4.9ns (10% to 90%); fDIN = 10MHz, PulseWidthDIN = 50ns 400 610 1000 ps tfVOD Fall time differential output voltage (80% to 20%) (Figure 4.) trDIN = 4.2ns (90% to 10%); fDIN = 10MHz, PulseWidthDIN = 50ns 400 610 1000 ps tPLHDIN0 Differential propagation delay time DIN0 (CLKIN to DOUT) (Low to High) (Note 2) (Figure 10.) trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=22MHz, PulseWidthDIN = 50ns 8ns tPHLDIN0 Differential propagation delay time DIN0 (CLKIN to DOUT) (High to Low) (Note 2) (Figure 10.) trDIN0-DIN7,CLKIN=4.2ns (90% to 10%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=22MHz, PulseWidthDIN = 50ns 8ns tPLHDIN7 Differential propagation delay time DIN7 (CLKIN to DOUT) (Low to High) (Note 2) (Figure 10.) trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=22MHz, PulseWidthDIN = 50ns 53 ns tPHLDIN7 Differential propagation delay time DIN7 (CLKIN to DOUT) (High to Low) (Note 2) (Figure 10.) trDIN0-DIN7,CLKIN=4.2ns (90% to 10%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=10MHz, PulseWidthDIN = 50ns 53 ns tOCD Differential propagation delay time (CLKIN to DOUT first positive edge) (Low to High) (Figure 10.) trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=10MHz, PulseWidthDIN = 50ns 11 ns tSU_CLK Set-up time (DIN0-DIN7, DV to CLKIN) (LH or HL to positive CLKIN edge) (Figure 11.) trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN= 4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=4 to 22MHz, PulseWidthDIN = 50ns 12 ns tH_CLK Hold time (CLKIN to DIN0- DIN7, DV) (positive CLKIN edge to LH or HL DIN,DV transition) (Figure 11.) trDIN0-DIN7,CLKIN=4.9ns (10% to 90%); tfDIN0-DIN7,CLKIN=4.2ns (90% to 10%); fDIN0-DIN7,CLKIN=4 to 22MHz, PulseWidthDIN = 50ns 10 ns tEN Enable delay time (EN to DOUT: tPLZ, tPHZ) (Figure 7.) trEN = 2.0ns (10% to 90%); tfEN = 2.0ns (90% to 10%) 20 µs tDIS Disable delay time (EN to DOUT: tPLZ, tPHZ) (Figure 7.) trEN = 2.0ns (10% to 90%); tfEN = 2.0ns (90% to 10%) 1000 ns fOPR Operating frequency parallel mode with DPLL BYP = GND, fDIN0-DIN7,CLKIN=4 to 27MHz PulseWidthDIN0,CLKIN = 50% trDIN0,CLKIN=3ns (10% to 90%); tfDIN0,CLKIN=3ns (90% to 10%) 427 MHz |
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