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MCP3008 Datasheet(PDF) 3 Page - Microchip Technology |
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MCP3008 Datasheet(HTML) 3 Page - Microchip Technology |
3 / 34 page © 2007 Microchip Technology Inc. DS21295C-page 3 MCP3004/3008 Analog Inputs Input Voltage Range for CH0 or CH1 in Single-Ended Mode VSS —VREF V Input Voltage Range for IN+ in pseudo-differential mode IN- — VREF+IN- Input Voltage Range for IN- in pseudo-differential mode VSS-100 — VSS+100 mV Leakage Current — 0.001 ±1 µA Switch Resistance — 1000 — Ω See Figure 4-1 Sample Capacitor — 20 — pF See Figure 4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage VIH 0.7 VDD —— V Low Level Input Voltage VIL — 0.3 VDD V High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL ——0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD Pin Capacitance (All Inputs/Outputs) CIN, COUT —— 10 pF VDD = 5.0V (Note 1) TAMB = 25°C, f = 1 MHz Timing Parameters Clock Frequency fCLK ——3.6 1.35 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time tHI 125 — — ns Clock Low Time tLO 125 — — ns CS Fall To First Rising CLK Edge tSUCS 100 — — ns CS Fall To Falling CLK Edge tCSD —— 0 ns Data Input Setup Time tSU —— 50 ns Data Input Hold Time tHD —— 50 ns CLK Fall To Output Data Valid tDO —— 125 200 ns ns VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 CLK Fall To Output Enable tEN —— 125 200 ns ns VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 CS Rise To Output Disable tDIS — — 100 ns See Test Circuits, Figure 1-2 CS Disable Time tCSH 270 — — ns D OUT Rise Time tR — — 100 ns See Test Circuits, Figure 1-2 (Note 1) D OUT Fall Time tF — — 100 ns See Test Circuits, Figure 1-2 (Note 1) ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TAMB = 25°C. Parameter Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”, for more information. |
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