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24LC256 Datasheet(PDF) 7 Page - Microchip Technology |
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24LC256 Datasheet(HTML) 7 Page - Microchip Technology |
7 / 26 page © 2005 Microchip Technology Inc. DS21203N-page 7 24AA256/24LC256/24FC256 FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS FIGURE 4-2: ACKNOWLEDGE TIMING Address or Acknowledge Valid Data Allowed to Change Stop Condition Start Condition SCL SDA (A) (B) (D) (D) (C) (A) SCL 9 8 7 6 5 4 3 2 1 123 Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. Receiver must release the SDA line at this point so the Transmitter can continue sending data. Data from transmitte r SDA Acknowledge Bit Data from transmitte r |
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