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24C32 Datasheet(PDF) 7 Page - Microchip Technology |
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24C32 Datasheet(HTML) 7 Page - Microchip Technology |
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7 / 14 page  2004 Microchip Technology Inc. DS21061H-page 7 24C32 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send- ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Next Operation NO YES 6.0 READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 6.1 Current Address Read The 24C32 contains an address counter that maintains the address of the last word accessed, internally incre- mented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read oper- ation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24C32 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C32 discontinues transmission (Figure 6-1). 6.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C32 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge. This termi- nates the write operation, but not before the internal address pointer is set. Then the master issues the con- trol byte again but with the R/W bit set to a one. The 24C32 will then issue an acknowledge and transmit the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24C32 to discontinue transmission (Figure 6-2). FIGURE 6-1: CURRENT ADDRESS READ CONTROL A C K S T A R T S T O P BYTE DATA n BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY A C K N O S P |
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