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ABV8069OC Datasheet(PDF) 2 Page - Abracon Corporation |
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ABV8069OC Datasheet(HTML) 2 Page - Abracon Corporation |
2 / 10 page (Preliminary) ABV8068/69 320-640MHz Low Phase Noise VCXO 30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 9/1/05 Page 2 OUTPUT ENABLE LOGICAL LEVELS Part # OE State 0 (Default) Output enabled ABV8068 (PECL) 1 Tri-state 0 Tri-state ABV8069 (LVDS) 1 (Default) Output enabled PIN DESCRIPTIONS Name TSSOP Pin number 3x3mm QFN Pin number Type Description VDDANA 1 11 P VDD for analog Circuitry. XIN 2 12 I Crystal input pin. (See Crystal Specifications on page 4). XOUT 3 13 O Crystal output pin. (See Crystal Specifications on page 4). DNC 4 14 - Do Not Connect OE_CTRL 5 15 I Output enable control pin. (See OE_CTRL Logic Levels above). VCON 6 16 I Voltage control input. GNDANA 7 1 P Ground for analog circuitry. LP 8 2 - LM 9 3 - Tuning inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between LP and adjacent LM pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. GNDBUF 10 4 P GND connection for output buffer circuitry. Q 11 5 O PECL or LVDS output. VDDBUF 12 6 P VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. QBAR 13 7 O Complementary PECL, LVDS output. GNDBUF 14 8 P GND connection for output buffer circuitry. DNC 15 9 - Do Not Connect DNC 16 10 - Do Not Connect |
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