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TMS320TCI6482ZTZ Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320TCI6482ZTZ Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 255 page  www.ti.com 1 Features TMS320TCI6482 Communications Infrastructure Digital Signal Processor SPRS246F – APRIL 2005 – REVISED MAY 2007 • High-Performance Fixed-Point DSP (TCI6482) • Four 1x Serial RapidIO® Links (or One 4x), v1.2 Compliant – 1.17- and 1-ns Instruction Cycle Time – 1.25-, 2.5-, 3.125-Gbps Link Rates – 850-MHz and 1-GHz Clock Rate – Message Passing, DirectIO Support, Error – Eight 32-Bit Instructions/Cycle Mgmt Extensions, Congestion Control – 8000 MIPS/MMACS (16-Bits) – IEEE 1149.6 Compliant I/Os – Commercial Temperature [0°C to 90°C] • 32-Bit DDR2 Memory Controller (DDR2-533 – Extended Temperature [-40 °C to 105°C] SDRAM) • TMS320C64x+™ DSP Core • EDMA3 Controller (64 Independent Channels) – Dedicated SPLOOP Instruction • 32-/16-Bit Host-Port Interface (HPI) – Compact Instructions (16-Bit) – Instruction Set Enhancements • 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface – Exception Handling Conforms to PCI Local Bus Specification (v2.3) • TMS320C64x+ Megamodule L1/L2 Memory • Two McBSPs Architecture: – 256K-Bit (32K-Byte) L1P Program Cache • 10/100/1000 Mb/s Ethernet MAC (EMAC) [Direct Mapped] – IEEE 802.3 Compliant – 256K-Bit (32K-Byte) L1D Data Cache – Supports Multiple Media Independent [2-Way Set-Associative] Interfaces (MII, GMII, RMII, and RGMII) – 16M-Bit (2096K-Byte) L2 Unified Mapped – 8 Independent TX and RX Channels RAM/Cache [Flexible Allocation] • Two 64-Bit General-Purpose Timers, – 256K-Bit (32K-Byte) L2 ROM Configurable as Four 32-Bit Timers – Time Stamp Counter • UTOPIA • 2 RSAs for CDMA Processing – UTOPIA Level 2 Slave ATM Controller – Dedicated RAKE, PATH_SEARCH and – 8-Bit Transmit and Receive Operations up RACH_SEARCH Instructions to 50 MHz per Direction – Transmit Processing Capability – User-Defined Cell Format up to 64 Bytes • Enhanced VCP2 • VLYNQ™ Port – Supports Over 694 7.95-Kbps AMR – Full Duplex Serial Bus – Programmable Code Parameters – Up to 4-Bit Transmit, 4-Bit Receive • Enhanced Turbo Decoder Coprocessor (TCP2) – Up to 125-MHz Operation – Supports up to Eight 2-Mbps 3GPP • 16 General-Purpose I/O (GPIO) Pins (6 Iterations) • System PLL and PLL Controller – Programmable Turbo Code and Decoding • Secondary PLL and PLL Controller, Dedicated Parameters to EMAC and DDR2 Memory Controller • Endianess: Little Endian, Big Endian • Advanced Event Triggering (AET) Compatible • 64-Bit External Memory Interface (EMIFA) • Trace-Enabled Device – Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and • IEEE-1149.1 (JTAG™) Synchronous Memories (SBSRAM, ZBT Boundary-Scan-Compatible SRAM) • 697-Pin Ball Grid Array (BGA) Package – Supports Interface to Standard Sync (ZTZ or GTZ Suffix), 0.8-mm Ball Pitch Devices and Custom Logic (FPGA, CPLD, • 0.09-µm/7-Level Cu Metal Process (CMOS) ASICs, etc.) • 3.3-/1.8-/1.5-/1.25-/1.2-V I/Os, – 32M-Byte Total Addressable External Memory Space 1.25-/1.2-V Internal • One Inter-Integrated Circuit (I2C) Bus Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2005–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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