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MH8S64DBKG-8 Datasheet(PDF) 5 Page - Mitsubishi Electric Semiconductor |
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MH8S64DBKG-8 Datasheet(HTML) 5 Page - Mitsubishi Electric Semiconductor |
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5 / 55 page  MH8S64DBKG -7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM MITSUBISHI LSIs ( / 55 ) MITSUBISHI ELECTRIC 17.Sep.1999 Preliminary Spec. Some contents are subject to change without notice. MIT-DS-0340-0.0 5 Serial Presence De tect Table II 31 Density of each bank on module 32MByte 08 36-61 Superset Information (may be used in future) option 00 62 SPD Revision 63 Checksum for bytes 0-62 Check sum for -8,-8L 45 64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF 72 Manufacturing location Miyoshi,Japan 01 Tajima,Japan 02 NC,USA 03 Germany 04 73-90 Manufactures Part Number MH8S64DBKG-8 4D483853363444424B472D38202020202020 MH8S64DBKG-8L 91-92 Revision Code PCB revision rrrr 93-94 Manufacturing date year/week code yyww 95-98 Assembly Serial Number serial number ssssssss 99-125 Manufacture Specific Data option 00 126 Intetl specification frequency 100MHz 64 127 Intel specification CAS# Latency support 128+ Unused storage locations open 00 4D483853363444424B472D384C2020202020 32 Command and Address signal input setup time 2ns 20 20 33 Command and Address signal input hold time 1ns 10 34 Data signal input setup time 2ns 35 Data signal input hold time 1ns 10 rev 1.2A 12 Check sum for -7,7L 05 MH8S64DBKG-7 4D483853363444424B472D374C2020202020 -7,7L CF -8,8L CD MH8S64DBKG-7L 4D483853363444424B472D37202020202020 |
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