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TDA3618AJR Datasheet(PDF) 6 Page - NXP Semiconductors

Part No. TDA3618AJR
Description  Multiple voltage regulator with switch and ignition buffers
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 6 page
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2001 May 02
6
Philips Semiconductors
Product specification
Multiple voltage regulator with
switch and ignition buffers
TDA3618AJR
FUNCTIONAL DESCRIPTION
The TDA3618AJR is a multiple output voltage regulator
with a power switch, intended for use in car radios with or
without a microcontroller. Because of the low-voltage
operation of the car radio, low-voltage drop regulators are
used in the TDA3618AJR.
Regulator 2 switches on when the backup voltage
exceeds 6.5 V for the first time and switches off again
when the output voltage of regulator 2 falls below 1.9 V
(this is far below an engine start). When regulator 2 is
switched on and its output voltage is within its voltage
range, the reset output is enabled to generate a reset to
the microcontroller. The reset cycle can be extended by an
external capacitor at pin CRES. This start-up feature is
included to secure a smooth start-up of the microcontroller
at first connection, without uncontrolled switching of
regulator 2 during the start-up sequence.
The charge of the backup capacitor can be used to supply
regulator 2 for a short period when the supply drops to 0 V
(the time depends on the value of the storage capacitor).
The output stages of regulators 1 and 3 have an extremely
low noise behaviour and good stability. These regulators
are stabilized by using small output capacitors.
When both regulator 2 and the supply voltage (VP > 4.5 V)
are available, regulators 1 and 3 can be operated by
means of the enable inputs (pins EN1 and EN3
respectively).
Pin HOLD is normally HIGH and is active LOW. Pin HOLD
is connected to an open collector NPN transistor and must
have an external pull-up resistor to operate. The HOLD
output is controlled by a LOW-voltage detection circuit
which, when activated, pulls the warning output LOW
(enabled). The detection outputs of the regulators are
connected to an OR gate inside the IC such that the hold
is activated (goes LOW) when the regulator voltages of
regulator 1 and/or regulator 3 are out of regulation for any
reason. Each regulator enable input controls its own
detection circuit, such that if a regulator is disabled or
switched off, the detection circuit for that regulator is
disabled.
The hold circuit is also controlled by the temperature and
load dump protection. Activating the temperature or load
dump protection causes a hold (LOW) during the time the
protection is activated. When all regulators are switched
off, pin HOLD is controlled by the battery line (pin VP),
temperature protection and load dump protection.
The hold output is enabled (LOW) at low battery voltages.
This indicates that it is not possible to get regulator 1 into
regulation when switching it on. The hold function includes
hysteresis to avoid oscillations when the regulator voltage
crosses the hold threshold. Pin HOLD also becomes LOW
when the switch is in foldback protection mode; see Fig.4
for a timing diagram. The hold circuit block diagram is
given in Fig.3.
The power switch can also be controlled by means of a
separate enable input (pin ENSW).
All output pins are fully protected. The regulators are
protected against load dump (regulators 1 and 3 switch off
at supply voltages >18 V) and short circuit (foldback
current protection).
The switch contains a current protection. However, this
protection is delayed at short-circuit by the reset delay
capacitor. During this time, the output current is limited to
a peak value of at least 3 and 2 A continuous (VP ≤ 18 V).
In the normal situation, the voltage on the reset delay
capacitor is approximately 3.5 V (depending on
temperature). The switch output is approximately
VP − 0.4 V. At operational temperature, the switch can
deliver at least 3 A. At high temperature, the switch can
deliver approximately 2 A. During an overload condition or
short-circuit (VSW <VP − 3.7 V), the voltage on the reset
delay capacitor rises 0.6 V above the voltage of
regulator 2. This rise time depends on the capacitor
connected to pin CRES. During this time, the switch can
deliver more than 3 A. The charge current of the reset
delay capacitor is typically 4
µA and the voltage swing
approximately 1.5 V. When regulator 2 is out of regulation
and generates a reset, the switch can only deliver 2 A and
will go into foldback protection without delay. At supply
voltages >17 V, the switch is clamped at 16 V maximum
(to avoid externally connected circuits being damaged by
an overvoltage) and the switch will switch off at load dump.
Interfacing with the microcontroller (simple full/semi on/off
logic applications) can be realized with two independent
ignition Schmitt triggers and ignition output buffers (one
open collector and one push-pull output). Ignition 1 output
is inverted.
The total timing diagrams are shown in Figs 4 and 5.




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