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MH8S64DBKG-6 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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MH8S64DBKG-6 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
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1 / 51 page  MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM MITSUBISHI LSIs ( / 51 ) MITSUBISHI ELECTRIC 27.Mar.2001 Preliminary Spec. Some contents are subject to change without notice. MIT-DS-0340-0.3 DESCRIPTION The MH8S64DBKG is 8388608 - word by 64-bit Synchronous DRAM module. This consists of eight industry standard 4Mx16 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules. FEATURES single 3.3V±0.3V power supply Fully synchronous operation referenced to clock rising edge Burst length- 1/2/4/8/Full Page(programmable) 4 bank operation controlled by BA0,1(Bank Address) /CAS latency- 2/3(programmable) APPLICATION main memory or graphic memory in computer systems Auto precharge / All bank precharge controlled by A10 Burst type- sequential / interleave(programmable) Column access - random LVTTL Interface Auto refresh and Self refresh 4096 refresh cycle /64ms 1 Utilizes industry standard 4M x 16 Sy nchronous DRAMs TSOP and industry standard EEPROM in TSSOP 144-pin (72-pin dual in-line package) (Front) (Back) 1 2 143 144 PCB Outline Frequency CLK Access Time -8,-8L 100MHz 6.0ns(CL=2) (Component SDRAM) 6.0ns(CL=3) 100MHz -7,-7L 133MHz 5.4ns(CL=3) -6,-6L Max. Clock frequency -6:133MHz,-7,8:100MHz |
Similar Part No. - MH8S64DBKG-6 |
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Similar Description - MH8S64DBKG-6 |
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