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LTC4215 Datasheet(PDF) 11 Page - Linear Technology

Part # LTC4215
Description  Hot Swap Controller with I2C Compatible Monitoring
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4215 Datasheet(HTML) 11 Page - Linear Technology

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LTC4215
11
4215fb
and SDAO (output). This simplifies applications using an
optoisolator driven directly from the SDAO output. An
application which uses optoisolation is shown in Figure
14. The I2C device address is decoded using the ADR0,
OPERATIO
ADR1 and ADR2 pins. These inputs have three states each
that decode into a total of 27 device addresses. ADR1 and
ADR2 are not available in the SSOP package; therefore,
those pins are NC in the address map.
APPLICATIO S I FOR ATIO
A typical LTC4215 application is in a high availability system
in which a positive voltage supply is distributed to power
individual cards. The device measures card voltages and
currents and records past and present fault conditions.
The system queries each LTC4215 over the I2C periodically
and reads status and measurement information.
A basic LTC4215 application circuit is shown in Figure 1.
The following sections cover turn-on, turn-off and various
faults that the LTC4215 detects and acts upon. External
component selection is discussed in detail in the Design
Example section.
Turn-On Sequence
The power supply on a board is controlled by using an
external N-channel pass transistor (Q1) placed in the power
path. Note that resistor RS provides current detection. Re-
sistors R1, R2 and R3 define undervoltage and overvoltage
levels. R5 prevents high frequency oscillations in Q1 and
R6 and C1 form an optional network that may be used to
provide an output dV/dt limited start-up.
Figure 1. Typical Application
+
UV
SENSE+
SENSE
LTC4215UFD
GATE
INTVCC
TIMER
GND
ADR2
ADR1
NC
ADR0
SOURCE
OV
ON
SDAI
SDAO
SCL
ALERT
FB
ADIN
GPIO
EN
SS
PLUG-IN
CARD
R5
10
R6
15k
C1
6.8nF
CSS
7.5nF
RS
0.005
Q1
FDC653N
R7
30.1k
1%
R8
3.57k
1%
VOUT
12V
R4
24k
4215 TA01a
CL
330
µF
CF
0.1
µF
R1
34k
1%
R2
1.02k
1%
R3
3.4k
1%
Z1
SA14A
BACKPLANE
GND
ALERT
SCL
SDA
VIN
12V
CTIMER
0.68
µF
C3
0.1
µF
VDD
Several conditions must be present before the external
MOSFET turns on. First the external supply, VDD, must
exceed its 2.84V undervoltage lockout level. Next the
internally generated supply, INTVCC, must cross its 2.64V
undervoltage threshold. This generates a 60µs to 120µs
power-on-reset pulse. During reset the fault registers are
cleared and the control registers are set or cleared as
described in the register section.
After a power-on-reset pulse, the LTC4215 goes through
the following turn-on sequence. First the UV and OV pins
indicate that input power is within the acceptable range,
which is indicated by bits C0-C1 in Table 4. Second, the EN
pin is externally pulled low. Finally, all of these conditions
must be satisfied for the duration of 100ms to ensure that
any contact bounce during insertion has ended.
When these initial conditions are satisfied, the ON pin is
checked and it’s state written to bit A3 in Table 2. If it is
high, the external MOSFET is turned on. If the ON pin is
low, the external MOSFET is turned on when the ON pin


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