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LTC4214-1CMS Datasheet(PDF) 8 Page - Linear Technology |
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LTC4214-1CMS Datasheet(HTML) 8 Page - Linear Technology |
8 / 32 page LTC4214-1/LTC4214-2 8 421412f VIN (Pin 1): Positive Supply Input. Connect this pin to the positive side of the supply via a resistor. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (5.1V), overriding UV and OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating a GATE ramp-up. If VIN drops below approximately 4.8V, GATE pulls low immediately. PWRGD (Pin 2): Power Good Status Output. At start-up, PWRGD latches low if DRAIN is below 1.232V and GATE is within 2.8V of VIN. PWRGD status is reset by UV, VIN (UVLO) or a circuit breaker fault timeout. This pin is internally pulled high by a 50 µA current source. SS (Pin 3): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/ dt. A 20x attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET’s drain current through the sense resistor during the soft-start current limiting. At the beginning of a start-up cycle, the SS capacitor (CSS) is ramped by a 22 µA current source. The GATE pin is held low until SS exceeds 20 • VOS = 0.2V. SS is internally shunted by a 73k resistor (RSS) which limits the SS pin voltage to 1.6V. This corresponds to an analog current limit SENSE voltage of 70mV. If the SS capacitor is omitted, the SS pin ramps from 0V to 1.6V in about 220 µs. The SS pin is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. SENSE (Pin 4): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor RS con- nected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (40 µA + 8 • IDRN) TIMER pull-up current. If SENSE exceeds VACL (70mV), the analog cur- rent limit amplifier pulls GATE down to regulate the MOSFET current at VACL/RS. In the event of a catastrophic short- circuit, SENSE may overshoot 70mV. If SENSE reaches VFCL (200mV), the fast current limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. VEE (Pin 5): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 50 µA current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV, OV, or a circuit breaker fault timeout. GATE is actively servoed to control the fault current as measured at SENSE. A compensation capacitor at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp-up after an overvoltage event or restart after a current limit fault. During GATE start-up, a second comparator detects if GATE is within 2.8V of VIN before PWRGD is set. DRAIN (Pin 7): Drain Sense Input. DRAIN measures the drain-source voltage of the external N-channel MOSFET switch for two purposes: first, a comparator detects when VDS < 1.232V and together with the GATE high compara- tor, controls the status of the PWRGD output. Second, if VDS is greater than the DRAIN clamp of approximately 4.2V (VDRNCL), the current through resistor RD is multi- plied by 8 and added to the TIMER’s 40 µA pull-up current during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating under conditions of high dissipation. OV (Pin 8): Overvoltage Input. The active high threshold at the OV pin is set at 3V with respect to VEE and exhibits 0.15V hysteresis. If OV > 3V, GATE pulls low. When OV returns below 2.85V, GATE start-up begins without an initial timing cycle. If an overvoltage condition occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after the overvoltage condition goes away. An overvoltage condition does not reset the PWRGD flag. The internal UVLO at VIN always overrides OV. A 1nF to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents glitches at the GATE pin. PI FU CTIO S |
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