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PLL650-02XC-R Datasheet(PDF) 5 Page - PhaseLink Corporation |
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PLL650-02XC-R Datasheet(HTML) 5 Page - PhaseLink Corporation |
5 / 6 page PLL650-02 Low EMI Network LAN Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 5 3. DC Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Operating Voltage VDD 2.97 3.63 V Input High Voltage VIH VDD /2 V Input Low Voltage VIL VDD /2 VDD /2 - 1 V Input High Voltage VIH For all Tri-level input VDD -0.5 V Input Low Voltage VIL For all Tri-level input 0.5 V Input High Voltage VIH For all normal input 2 V Input Low Voltage VIL For all normal input 0.8 V Output High Voltage VOH IOH = -25mA 2.4 V Output Low Voltage VOL IOL = 25mA 0.4 V Output High Voltage At CMOS Level VOH IOH = -8mA VDD -0.4 V Operating Supply Current IDD No Load 35 mA Short-circuit Current IS ±100 mA Nominal output current* Iout CMOS output level 35 40 mA Nominal output current* Iout TTL output level 20 25 mA Internal pull-up resistor Rup Pins 6,8 60 k Ω Internal pull-up resistor Rup Pin 3 120 k Ω *: SDRAM output strengths are doubled (i.e. min. CMOS level is 70mA, typ. CMOS level is 80mA) |
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Similar Description - PLL650-02XC-R |
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