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PL560-09QCR Datasheet(PDF) 9 Page - PhaseLink Corporation |
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PL560-09QCR Datasheet(HTML) 9 Page - PhaseLink Corporation |
9 / 15 page Analog Frequency Multiplier PL560-xx VCXO Family 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:02-09-07 Page 9 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, DC VI GND-0.5 VDD+0.5 V Output Voltage, DC VO GND-0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature, Industrial Temperature TA_I -40 +85 °C Ambient Operating Temperature, Commercial Temperature TA_C 0 +70 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C Input Static Discharge Voltage Protection 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. PECL ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (with loaded outputs) IDD Fout = 622 MHz 75 80 mA Operating Voltage VDD 2.25 3.63 V Output Clock Duty Cycle @ Vdd – 1.3V 45 50 55 % Short Circuit Current ±50 mA Output High Voltage VOH RL = 50 Ω to (VDD – 2V) VDD – 1.025 V Output Low Voltage VOL VDD – 1.620 V Clock Rise Time tr @20/80% 0.25 0.45 ns Clock Fall Time tf @80/20% 0.25 0.45 ns PECL Transition Time Waveform OUT OUT 20% 80% tR tF DUTY CYCLE 45 - 55% 55 - 45% OUT OUT 50Ω 50Ω PECL Levels Test Circuit VDD 2.0V 50% OUT OUT t SKEW PECL Output Skew |
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