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LTC1257IN8 Datasheet(PDF) 8 Page - Linear Technology |
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LTC1257IN8 Datasheet(HTML) 8 Page - Linear Technology |
8 / 12 page 8 LTC1257 Serial Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first and the LSB last. The DAC register loads the data from the shift register when LOAD is pulled low, and remains transpar- ent until LOAD is pulled high and the data is latched. An internal 5V regulator provides the supply for the digital logic. By limiting the internal digital signal swings to 5V, digital noise is reduced. The buffered output of the 12-bit shift register is available on the DOUT pin which will swing from GND to VCC. Multiple LTC1257s may be daisy chained together by connecting the DOUT pin to the DIN pin of the next chip, while the clock and load signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the LOAD signal is pulled low to update all of them simultaneously. The maximum clocking rate is 1.4MHz. Reference The LTC1257 includes an internal 2.048V reference, mak- ing 1LSB equal to 500 µV. The internal reference output is turned off when the pin is forced above the reference voltage, allowing an external reference to be connected to the reference pin. The external reference must be greater than 2.475V and less than VCC – 2.7V, and be capable of driving the 10k minimum DAC resistor ladder. If the reference output is driving a large capacitive load, a series resistor must be added to insure stability. For any capacitive load greater than 1 µF, a 10Ω series resistor will suffice. Voltage Output The LTC1257 voltage output is able to pull within 2.7V of VCC while sourcing 2mA. A internal NMOS transistor with a 200 Ω equivalent impedance pulls the output to ground. The output is protected against short circuits and is able to drive up to a 500pF capacitive load without oscillation. If digital noise on the output causes a problem, a simple 100 Ω, 0.1µF RC circuit can be used to filter the noise. DAC with External Reference Filtering VREF and VOUT 0.1 µF 0.1 µF 1 µF VCC VCC VREF GND VOUT VOUT DIN CLK LOAD DOUT LTC1257 1257 TA06 10 Ω 5% 100 Ω 5% µP 15V 0.1 µF CONTROL OUTPUT VCC VREF GND VOUT DIN CLK LOAD DOUT LTC1257 1257 TA03 IN OUT GND LT1021-10 OPERATIO TYPICAL APPLICATIO S |
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