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PLL500-17TCLR Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL500-17TCLR Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 6 page PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/08/06 Page 2 DIE PAD LAYOUT DIE SPECIFICATIONS Name Value Size 39 x 32 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil PACKAGE PIN and DIE PAD ASSIGNMENT Pin# Die Pad Position Name SOP-8 SOT23-6 X ( µm) Y ( µm) Type Description XIN 1 6 94.183 768.599 I Crystal input pin. VDD 2 5 94.157 605.029 P VDD power supply pin. Only one VDD pin is nec- essary. VCON 3 4 94.183 331.756 I Frequency control voltage input pin. GND 4 2 94.193 140.379 P Ground pin. CLK 5 3 715.472 203.866 O Output clock pin. VDD 6 - 715.307 455.726 P VDD power supply pin. Only one VDD pin is nec- essary. OE 7 - 715.472 626.716 I Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. XOUT 8 1 476.906 888.881 I Crystal output pin. Ref Clock input. * OE (Output Enable) pin is not available in SOT-26 package, the output will always be enabled by the build in pull-up resister. 5 Y X (0,0) (812,986) 32 mil 8 6 2 3 4 7 DIE ID: PLL500-17: C500A0404-04A 1 XIN VDD CLK GND VCON XOUT OE^ VDD Note: ^ denotes internal pull up |
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