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PLL502-02HSILR Datasheet(PDF) 1 Page - PhaseLink Corporation |
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PLL502-02HSILR Datasheet(HTML) 1 Page - PhaseLink Corporation |
1 / 4 page PLL502-02 Low Phase Noise VCXO (24MHz to 50MHz) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/05 Page 1 FEATURES • Low phase noise VCXO output for the 24MHz to 50MHz range (-130 dBc at 10kHz offset). • CMOS output. • 12 to 25MHz crystal input. • Integrated variable capacitors. • Selectable High Drive (30mA) or Standard Drive (10mA) output. • Wide pull range (+/- 250 ppm typ.). • Low jitter (RMS): 3ps period (1 sigma). • 3.3V operation. • Available in 8-Pin SOIC. DESCRIPTION The PLL502-02 is a low cost, high performance, low phase noise VCXO, providing less than -130dBc at 10kHz offset in the 24MHz to 50MHz operating range. The very low jitter (3 ps RMS period jitter) makes this chip ideal for applications requiring volt- age controlled frequency sources. Input crystal can range from 12 to 25MHz (fundamental resonant mode). PIN CONFIGURATION OUTPUT RANGE MULTIPLIER FREQUENCY RANGE OUTPUT BUFFER x2 24 - 50MHz CMOS BLOCK DIAGRAM Reference Divider Phase Comparator Charge Pump Loop Filter VCO VCO Divider XTAL OSC OE XIN XOUT CLK VCON VARICAP 1 2 3 45 6 7 8 XOUT N/C VCON GND XIN VDD CLK N/C |
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