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PLL520-07 Datasheet(PDF) 1 Page - PhaseLink Corporation

Part # PLL520-07
Description  Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
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Manufacturer  PLL [PhaseLink Corporation]
Direct Link  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PLL520-07 Datasheet(HTML) 1 Page - PhaseLink Corporation

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PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal.
• Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 800MHz (4x
multiplier), or 800MHz – 1GHz (PLL520-09
TSSOP only, 8x multiplier).
• High yield design supports up to 2pF stray
capacitance at 200MHz.
• CMOS (Standard drive PLL520-07 or Selectable
Drive PLL520-06), PECL (Enable low PLL520-08
or Enable high PLL520-05) or LVDS output
(PLL520-09).
• Integrated variable capacitors.
• Supports 3.3V-Power Supply.
• Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: PLL520-06 only available in 3x3mm.
Note: PLL520-07 only available in TSSOP.
DESCRIPTION
The PLL520-05/-06/-07/-08/-09 is a family of VCXO
ICs specifically designed to pull high frequency
fundamental crystals. Their design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. They
achieve very low current into the crystal resulting in
better overall stability. Their internal varicaps allow
an on chip frequency pulling, controlled by the
VCON input.
BLOCK DIAGRAM
PIN CONFIGURATION
(Top View)
^: Internal pull-up
*: PLL520-06 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
Output enabled
PLL520-08
1
Tri-state
0
Tri-state
PLL520-05
PLL520-06
PLL520-07
PLL520-09
1 (Default)
Output enabled
OE input: Logical states defined by PECL levels for PLL520-08
Logical states defined by CMOS levels for PLL520-05/-06/-
07/-09
XIN
XOUT
OE
Q
VCON
Q
PLL by-pass
SEL
PLL
(Phase
Locked
Loop)
Oscillator
Amplifier
w/
integrated
varicaps
1
2
3
4
5
6
7
8
VDD
9
10
11
12
13
14
15
16
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
P520-0x
GND
VDD
CLKT
CLKC
XOUT
XIN
SEL2^
OE
4
16
15
14
13
12
11
10
9
8
7
6
5
12
3


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