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PL580-35QCL Datasheet(PDF) 5 Page - PhaseLink Corporation |
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PL580-35QCL Datasheet(HTML) 5 Page - PhaseLink Corporation |
5 / 10 page (Preliminary) PL580-35/37/38/39 38MHz-320MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/06 Page 5 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS 38MHz<Fout<100MHz 65/45/30 Supply Current, Dynamic (with Loaded Outputs) IDD PECL/LVDS/CMOS 100MHz<Fout<320MHz 80/60/40 mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) 45 45 45 50 50 50 55 55 55 % Short Circuit Current ±50 mA Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. 5. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS 155.52MHz 0.4 0.5 Integrated jitter RMS Integrated 12 kHz to 20 MHz 311.04MHz 0.4 0.5 ps 77.76MHz 2.5 4 155.52MHz 3 5 Period jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. 311.04MHz 4 7 ps 77.76MHz 18 30 155.52MHz 20 30 Period jitter Peak-to- Peak With capacitive decoupling between VDD and GND. Over 10,000 cycles. 311.04MHz 25 35 ps 6. Phase Noise Specifications PARAMETERS FREQ. @10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M UNITS 77.76MHz -66 -96 -124 -134 -132 -145 -149 155.52MHz -62 -92 -120 -132 -128 -144 -150 Phase Noise relative to carrier (typical) 311.04MHz -59 -86 -116 -129 -124 -140 -148 dBc/Hz Note: Phase Noise measured at VCON = 0V. 7. CMOS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS IOH VOH= VDD-0.4V, VDD=3.3V 30 mA Output drive current IOL VOL = 0.4V, VDD = 3.3V 30 mA Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 0.7 ns Output Clock Rise/Fall Time 20%-80% with 50Ω Load 0.3 ns |
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