11

LT1191

+

–

LT1191 • TA14

+V

+V

3

2

1

8

5

BAL

BAL

SHDN

6

*

7

4

*SUBSTRATE DIODE, DO NOT FORWARD BIAS

SI PLIFIED SCHE ATIC

J8 1298

0.014 – 0.026

(0.360 – 0.660)

0.200

(5.080)

MAX

0.015 – 0.060

(0.381 – 1.524)

0.125

3.175

MIN

0.100

(2.54)

BSC

0.300 BSC

(0.762 BSC)

0.008 – 0.018

(0.203 – 0.457)

0

° – 15°

0.045 – 0.068

(1.143 – 1.727)

FULL LEAD

OPTION

0.023 – 0.045

(0.584 – 1.143)

HALF LEAD

OPTION

CORNER LEADS OPTION

(4 PLCS)

0.045 – 0.065

(1.143 – 1.651)

0.005

(0.127)

MIN

0.405

(10.287)

MAX

0.220 – 0.310

(5.588 – 7.874)

12

3

4

87

65

0.025

(0.635)

RAD TYP

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE

OR TIN PLATE LEADS

PACKAGE DESCRIPTIO

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

OBSOLETE PACKAGE

J8 Package

8-Lead CERDIP (Narrow .300 Inch, Hermetic)

(Reference LTC DWG # 05-08-1110)