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DS4026S+QCN Datasheet(PDF) 9 Page - Maxim Integrated Products |
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DS4026S+QCN Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 12 page The output driver is a CMOS square-wave output with symmetrical rise and fall time. The temperature sensor provides a 12-bit temperature reading with a resolution of 0.0625°C. The sensor is in continuous conversion mode unless the DCOMP bit in the control register is set to disable temperature updates. The controller coordinates the conversion of tempera- ture into digital codes. When the temperature reading is different from the previous one or the frequency tuning register is changed, the controller looks up the two cor- responding capacitance trim codes from the lookup table at a 0.5°C increment. The trim codes are interpo- lated to 0.0625°C resolution. The result is added with the tuning value from the fre- quency tuning register and loaded into the DAC regis- ters to adjust voltage output. The monotonic DAC provides an analog voltage based on temperature compensation to drive the variable capacitor. The DS4026 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code fol- lowed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. Address Map Disable Compensation Update (DCOMP) DCOMP is bit 7 of the frequency tuning register (see the Frequency Tuning Register (00h–01h), POR = 00h table). When set to logic 1, this bit’s temperature-com- pensation function is disabled. This disabling prevents the variable capacitor in the oscillator block from changing. However, the temperature register still per- forms temperature conversions. The temperature trim code from the last temperature conversion before DCOMP is enabled is used for temperature compensa- tion. The FTUNE registers are still functional when DCOMP is disabled. The frequency tuning registers adjust the base frequen- cy. The frequency tuning value is represented in two’s complement data. Bit 6 of FTUNEH is the sign, bit 5 is the MSB, and bit 0 of FTUNEL is the LSB (see Table 1). When the tuning register low (01h) is programmed with a value, the next temperature update cycle sums the programmed value with the factory compensated value. This allows the user to digitally control the base frequency using the I2C protocol. These frequency tuning register bits allow the tuning of the base frequency. Each bit typically represents about 1ppb (typ). For FTUNEH = 3Fh and FTUNEL = FFh, the device pushes the base frequency by approx- imately +15ppm. 12.8MHz to 51.84MHz TCXO _____________________________________________________________________ 9 Frequency Tuning Register (00h–01h), POR = 00h ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h DCOMP Sign Data Data Data Data Data Data POR 0 0 0 000 00 01h Data Data Data Data Data Data Data Data POR 0 0 0 000 00 Temperature Register (02h–03h) ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 02h Sign Data Data Data Data Data Data Data POR 0 0 0 000 00 03h Data Data Data Data 0 0 0 0 POR 0 0 0 000 00 |
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