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SST55LD019M-45-C-TQWE Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc |
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SST55LD019M-45-C-TQWE Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc |
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10 / 59 page  10 Advance Information ATA Flash Disk Controller SST55LD019M ©2005 Silicon Storage Technology, Inc. S71312-01-000 12/06 TABLE 3-1: Pin Assignments (1 of 4) Symbol Pin No. Pin Type I/O Type1 Name and Functions 100-TQFP 85- VFBGA 84- TFBGA Host Side Interface A2 53 B2 J8 I I1Z A[2:0] are used to select one of eight registers in the Task File. A1 22 D9 G3 A0 23 D8 H1 D15 65 D3 F8 I/O I1Z/O2 D[15:0] Data bus D14 66 E2 E10 D13 67 E3 E9 D12 68 F2 E8 D11 70 F3 D10 D10 71 G1 D9 D9 72 G2 C10 D8 73 G3 D8 D7 3 J9 C3 D6 4 H10 C4 D5 5 H9 B2 D4 6 H8 D4 D3 8 G9 C2 D2 9 G8 D3 D1 10 F10 C1 D0 11 F9 D2 DMACK 20 E8 G2 I I2U DMA Acknowledge - input from host DMARQ 14 F8 E3 O O1 DMA Request to host CS1FX# 24 C10 H2 II2Z CS1FX# is the chip select for the task file registers CS3FX# 52 B1 K9 CS3FX# is used to select the alternate status register and the Device Control register. CSEL 56 C3 J10 I I1U This internally pulled-up signal is used to configure this device as a Master or a Slave. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. The pin setting should remain the same from Power-on to Power-down. IORD# 19 E9 F1 II2Z This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the chip. IOWR# 57 D1 H9 The I/O Write strobe pulse is used to clock I/O data into the chip. IOCS16# 55 C2 H8 O O2 This output signal is asserted low when the device is indicating a word data transfer cycle. INTRQ 21 D10 G1 O O1 This signal is the active high Interrupt Request to the host. PDIAG# 54 C1 J9 I/O I1U/O1 The Pass Diagnostic signal in the Master/Slave handshake protocol. DASP# 75 H2 B10 I/O I1U/O6 The Drive Active/Slave Present signal in the Master/Slave handshake protocol. RESET# 1 K10 A2 I I2U This input pin is the active low hardware reset from the host. |
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