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SST25VF010 Datasheet(PDF) 4 Page - Silicon Storage Technology, Inc |
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SST25VF010 Datasheet(HTML) 4 Page - Silicon Storage Technology, Inc |
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4 / 22 page  4 Data Sheet 1 Mbit SPI Serial Flash SST25VF010 ©2006 Silicon Storage Technology, Inc. S71233-05-000 1/06 PRODUCT IDENTIFICATION MEMORY ORGANIZATION The SST25VF010 SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay blocks. DEVICE OPERATION The SST25VF010 is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF010 supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. TABLE 2: PRODUCT IDENTIFICATION Address Data Manufacturer’s ID 00000H BFH Device ID SST25VF010 00001H 49H T2.0 1233 |
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