 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SST29VE010 Datasheet(PDF) 3 Page - Silicon Storage Technology, Inc |
|
||||||||||||||||||||||||||||||
SST29VE010 Datasheet(HTML) 3 Page - Silicon Storage Technology, Inc |
|
|
3 / 30 page  Data Sheet 1 Mbit Page-Write EEPROM SST29EE010 / SST29VE010 3 ©2005 Silicon Storage Technology, Inc. S71061-11-000 9/05 Write Operation Status Detection The SST29EE/VE010 provide two software means to detect the completion of a Write cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising WE# or CE# whichever occurs first, which ini- tiates the internal Write cycle. The actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- tion is valid. Data# Polling (DQ7) When the SST29EE/VE010 are in the internal Write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. See Fig- ure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Toggle Bit (DQ6) During the internal Write cycle, any consecutive attempts to read DQ6 will produce alternating ‘0’s and ‘1’s, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. The initial read of the Toggle Bit will typically be a “1”. Data Protection The SST29EE/VE010 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. Software Data Protection (SDP) The SST29EE/VE010 provide the JEDEC approved optional Software Data Protection scheme for all data alter- ation operations, i.e., Write and Chip-Erase. With this scheme, any Write operation requires the inclusion of a series of three-byte load operations to precede the data loading operation. The three-byte load sequence is used to initiate the Write cycle, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. The SST29EE/VE010 are shipped with the Software Data Protection disabled. The software protection scheme can be enabled by apply- ing a three-byte sequence to the device, during a page- load cycle (Figures 5 and 6). The device will then be auto- matically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See Table 4 for the specific software command codes and Figures 5 and 6 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 9 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~300 µs. SST recommends Software Data Protection always be enabled. See Figure 17 for flowcharts. The SST29EE/VE010 Software Data Protection is a global command, protecting all pages in the entire memory array once enabled. Therefore using SDP for a single Page- Write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled. Single power supply reprogrammable nonvolatile memo- ries may be unintentionally altered. SST strongly recom- mends that Software Data Protection (SDP) always be enabled. The SST29EE/VE010 should be programmed using the SDP command sequence. |
Similar Part No. - SST29VE010 |
|
Similar Description - SST29VE010 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
