ASAHI KASEI

[AK93C45B/55B/65B/75B]

DAM04E-02

2003/05

- 5 -

WRITE

The write instruction is followed by 16 bits of data to be written into the specified address. After the

last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the

SK clock.

This falling edge of the CS initiates the self-timed programming cycle.

The DO

indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs).

DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the

register at the address specified in the instruction has been written with the new data pattern

contained in the instruction and the part is ready for a next instruction.

WRITE (AK93C45B)

*Address bit A7 becomes a "don't care" for AK93C55B.

WRITE (AK93C55B/65B)

WRITE (AK93C75B)

Hi-Z

0

tE/W

CS

SK

DI

DO

Start Bit

Op code

tCS

Busy

Ready

AK93C75B output a logic "1" (Ready status),

if previous instruction is WRITE.

D0

1

2

3

4

5

14

15

27

28

29

D1

D2

D14

D15

A0

A1

A8

1

0

1

0

X: Don't care

X

12

13

Hi-Z

0

tE/W

CS

SK

DI

DO

Start Bit

Op code

tCS

Busy

Ready

AK93C55B/65B output a logic "1" (Ready status),

if previous instruction is WRITE.

D0

1

2

3

4

5

10

11

12

13

25

26

27

D1

D2

D14

D15

A0

A1

A6

1

0

1

0

A7

X /

X: Don't care

Hi-Z

0

tE/W

CS

SK

DI

DO

Start Bit

Op code

tCS

Busy

Ready

AK93C45B output a logic "1" (Ready status),

if previous instruction is WRITE.

D0

1

2

3

4

5

8

9

10

11

23

24

25

D1

D2

D14

D15

A0

A1

A4

A5

1

0

1

0