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AK93C45CL Datasheet(PDF) 9 Page - Asahi Kasei Microsystems |
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AK93C45CL Datasheet(HTML) 9 Page - Asahi Kasei Microsystems |
9 / 16 page ASAHI KASEI [AK93C45C/55C/65C] DAM06E-01 2005/10 - 9 - READ The read instruction is the only instruction which outputs serial data on the DO pin. Following the Start bit, first Op code and address are decoded, then the data from the selected memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from the selected memory location. The output data changes are synchronized with the rising edges of the serial clock (SK). The data in the next address can be read sequentially by continuing to provide clock. The address automatically cycles to the next higher address after the 16bit data shifted out. When the highest address is reached, the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely. READ (AK93C45C) READ (AK93C55C) READ (AK93C65C) AK93C45C output a logic "1" (Ready status), if previous instruction is W RITE, PAGE WRITE, WRAL. address[A5–A0]+1 Hi-Z Hi-Z Dummy Bit address[A5–A0] 0 CS SK DI DO Start bit Op code D0 1 2 3 4 5 10 11 D14 D15 A0 A1 A4 0 1 1 0 25 26 40 41 D15 D1 D0 0 8 9 A5 AK93C55C output a logic "1" (Ready status), if previous instruction is W RITE, PAGE WRITE, WRAL. address[A6–A0]+1 Hi-Z Hi-Z Dummy Bit address[A6–A0] 0 CS SK DI DO Start bit Op code D0 1 2 3 4 5 12 13 D14 D15 A0 A1 A6 0 1 1 0 27 28 42 43 D15 D1 D0 0 X: Don't care 10 11 X AK93C65C output a logic "1" (Ready status), if previous instruction is W RITE, PAGE WRITE, WRAL. address[A7–A0]+1 Hi-Z Hi-Z Dummy Bit address[A7–A0] 0 CS SK DI DO Start bit Op code D0 1 2 3 4 5 12 13 D14 D15 A0 A1 A6 0 1 1 0 27 28 42 43 D15 D1 D0 0 10 11 A7 |
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