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TUSB6020ZQE Datasheet(PDF) 8 Page - Texas Instruments |
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TUSB6020ZQE Datasheet(HTML) 8 Page - Texas Instruments |
8 / 12 page www.ti.com Vbat Ext. Pwr. Mgmt: Vio (1.8 V) Ext Host: GPIOn TPS65030: EN2 (3.3 V, 1.5 V) TUSB6020: CPEN TPS65030: EN1 (5 V) TUSB6020: SWEN TPS65030: SW_EN (Vbat/Vbus) TPS65030: Pgood TUSB6020: RSTn TPS65030: Vout3 (1.5 V) TPS65030: Vout2 (3.3 V) TUSB6020: INT Ext Host: ExtInt/GPIOn TUSB6020: IO Interface Status TUSB6020: GPIO7 (Host Mode Select) TPS65030: TEST TUSB6020: GPIO6 (Reference Clock Select) Signal state cannot be ensured. Signal state is stable and valid. NOTE: Host mode and reference clock source selection is latched on RSTn rising edge. No external components are required to select NOR flash host mode and CLKIN as a reference clock source. Pulled down by Host Processor internal pulldown resistor Ext. Host GPIOn configured as output Ext. Host GPIOn enabled by SW IOINTERFACEISNOT INITIALIZED IOINTERFACEISINITIALIZED Pulled up by TUSB6020 GPIO7 internal pullup resistor (NOR FLASH Mode is selected) Pulled up by TUSB6020 GPIO6 internal pullup resistor (CLKIN is selected reference clock source) Pulled high by TUSB6020 internal pullup TUSB6020 sets INT low to indicate device is reday DEVICE PEAK POWER CONSUMPTION ESTIMATE INPUT CLOCK REQUIREMENTS TUSB6020 USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER SCPS170C – JANUARY 2007 – REVISED JULY 2007 APPLICATION INFORMATION (continued) Figure 1. System Power-Up Sequence POWER SUPPLY RESET STATE NORMAL STATE IDLE(1) 1.5 V 25 mA 110 mA 25 mA if XI is used as reference clock source 1.8 V 60 mA 80 μA 18 mA if CLKIN is used as reference clock source 3.3 V 10 mA 22 mA (1) In the idle state, device power consumption, including the companion power-management device (TPS65030), should not exceed 100 μA. PARAMETER VALUE Normal clock frequency 19.200, 24.000, or 48.000 MHz Frequency accuracy ±100 ppm Minimum rise/fall time 5 ns (10% to 90%) Voltage level 1.8 V Input clock type Square wave Duty cycle 40% to 60% Input capacitance loading 4 pF –95 dBc at 1 MHz Jitter –120 dBc at 100 MHz 8 Submit Documentation Feedback |
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