Philips Semiconductors

Product specification

SG3524

SMPS control circuit

1994 Aug 31

4

TIMING CAPACITOR VALUE (C–)–(

µF)

10

5

3

2

1.0

0.5

0.3

.001 .002

.005

.01 .02

.05

1

SL00178

Figure 5. Output Stage Dead Time as a Function of the Timing

Capacitor Value

100

50

20

10

5

2

1

100

50

20

10

5

200 5001ms2ms

OSCILLATOR PERIOD (

µs)

SL00179

Figure 6. Oscillator Period

FREQUENCY - (Hz)

80

60

40

20

0

10

100

1k

10k

100k

1M

10M

RL = RESISTANCE FROM

PIN 9 TO GND

RL = 30kΩ

RL = 100kΩ

RL = 1MΩ

RL = 30MΩ

RL = 300kΩ

SL00180

Figure 7. Amplifiers Open-Loop Gain as a Function of

Frequency and Loading on Pin 9

Oscillator

While this uses more current than a series-connected RC, it

provides a linear ramp voltage on the capacitor which is also used

as a reference for the comparator. The charging current is equal to

3.6 V

pulse is used (among other things) as a blanking pulse to both

outputs to insure that there is no possibility of having both outputs

on simultaneously during transitions. This output dead time

relationship is shown in Figure 5. A pulse width below approximately

0.5

µs may allow false triggering of one output by removing the

blanking pulse prior to the flip-flop’s reaching a stable state. If small

by adding a shunt capacitance (

≅100pF) to ground at the oscillator

output. [(Note: Although the oscillator output is a convenient

oscilloscope sync input, the cable and input capacitance may

increase the blanking pulse-width slightly.)] Obviously, the upper

limit to the pulse width is determined by the maximum duty cycle

Note that for series regulator applications, the two outputs can be

connected in parallel for an effective 0-90% duty cycle and the

frequency of the oscillator is the frequency of the output. For

push-pull applications, the outputs are separated and the flip-flop

divides the frequency such that each output’s duty cycle is 0-45%

and the overall frequency is one-half that of the oscillator.

External Synchronization

If it is desired to synchronize the SG3524 to an external clock, a

pulse of

≅+3V may be applied to the oscillator output terminal with

considerations of pulse-width apply. The impedance to ground at

this point is approximately 2k

Ω.

If two or more SG3524s must be synchronized together, one must

longer period than the master with the added requirement that

together will insure that the master output pulse—which occurs first

and has a wider pulse width—will reset the slave units.

Error Amplifier

This circuit is a simple differential input transconductance amplifier.

The output is the compensation terminal, Pin 9, which is a

A

8 I

2kT

[ 0.002R

L

and can easily be reduced from a nominal of 10,000 by an external

shunt resistance from Pin 9 to ground, as shown in Figure 7.

In addition to DC gain control, the compensation terminal is also the

place for AC phase compensation. The frequency response curves

of Figure 7 show the uncompensated amplifier with a single pole at

approximately 200Hz and a unity gain crossover at 5MHz.

Typically, most output filter designs will introduce one or more

additional poles at a significantly lower frequency. Therefore, the

best stabilizing network is a series RC combination between Pin 9

and ground which introduces a zero to cancel one of the output filter

poles. A good starting point is 50k

Ω plus 0.001µF.